Description: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder
“double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These
cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic. Platform: |
Size: 244736 |
Author:丁一 |
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Description: HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architecture based on HEVC is presented. By the analysis of the architecture design and adopting the area-saved and pipelined one, the Verilog HDL code is designed as well as logical simulation and performance analysis. Platform: |
Size: 5120 |
Author:毕翔宇 |
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Description: 标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作-Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA Platform: |
Size: 6144 |
Author:li yi |
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Description: coloecheck VGA格式标准色卡生成，可支持任意分辨率设置 verilog-colorchecker VGA format standard color card production, can support any resolution settings Platform: |
Size: 1024 |
Author:周召涛 |
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